This invention relates to VLSI logic and memory circuits. Specifically, it relates to suppression of effects of leakage current in selected logic paths of logic circuits and selected SRAM cells and sense amplifiers of memory circuits.
Leakage currents, such as standby, gate-to-body and bipolar leakage, in VLSI memory and logic circuits negatively affect performance and power efficiency. Excessive initial-cycle parasitic bipolar current in partially depleted (PD) Silicon-On-Insulator (SOI) circuits is known to degrade the noise margin and cause incorrect logic states, especially in pass gate logic. Recently, it has been shown that bipolar leakage current in non-selected cells on a bit column can cause degradation in read and write performance of PD SOI SRAM cells. As the technology scales, gate-to-body tunneling current through thin gate oxide layers can affect performance of PD SOI SRAM cells, especially at lower temperatures. For example, the gate-to-body tunneling current may charge and/or discharge a floating-body of a PD SOI device, and change the body voltage and threshold voltage, Vt, affecting circuit operation.
In an SRAM circuit, a sense amplifier senses bit differentials of true and complementary bitlines. Current leakage can cause degradation in sensing performance of sense amplifiers.
In a logic circuit, a critical path, which is the slowest path of the logic circuit, limits the speed of the logic circuit. The speed of the critical path limits the speed of the logic circuit. By increasing power voltage for increasing the speed of signal(s) traversing the critical path relative to other paths of the circuit, the speed of the logic circuit is increased. However, an increased power voltage may result in increased current leakage and associated negative effects.
Accordingly, a need exists for a system and method for reducing the effects of parasitic bipolar current during read operations in SRAM cells.
Furthermore, a need exists for system and method to vary power supply voltages and ground supply voltages to SRAM cells to suppress current leakage and improve the performance of the SRAM cells.
A need further exists for a system and method to vary power supply voltages to sense amplifiers for suppressing current leakage and improving performance.
In addition, a need exists for a system and method to vary pre-charge voltage levels of bitlines for suppressing current leakage and improving performance.
Finally, a need exists for a system and method to increase the speed of signal(s) traversing the critical path of a logic circuit relative to other paths of the logic circuit by increasing the power supply voltage provided to the logic gates of the critical path relative to the logic gates of the other paths of the logic circuit, while minimizing current leakage.
An aspect of the present invention is to provide a system and method for reducing the effects of parasitic bipolar current during read operations in SRAM cells.
Another aspect of the present invention is to provide a system and method to vary power supply voltage and ground supply voltage to SRAM cells for suppressing current leakage and improving the performance.
A further aspect of the present invention is to provide a system and method to vary power supply voltage to sense amplifiers for suppressing current leakage and improving the performance of the SRAM cells.
An additional aspect of the present invention is to vary pre-charge voltage levels of bitlines for suppressing current leakage and improving performance.
Finally, an aspect of the present invention is to vary the power supply voltage provided to logic gates of the critical path of a logic circuit relative to the other logic gates of the logic circuit, while minimizing current leakage.
Accordingly, an SRAM system is provided and includes at least one circuit receiving a first power voltage, and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit of the system. The system is one of a memory array and a logic system, the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. Furthermore, a method for providing a power supply voltage to at least one circuit of a system is provided. The method includes the steps of providing a first power supply voltage to the at least one circuit of the system, and providing a second power supply voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system, and the at least one selected circuit is one of a selected memory cell, a sense amplifier and a critical path of the logic system.